PIC16C58B-04/SS【PDF 84/194 页】IC MCU OTP 2KX12 20SSOP

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Sheet目录3889

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PIC18F2450/4450

DS39760A-page 172

Advance Information

2006 Microchip Technology Inc.

15.4.2

EUSART SYNCHRONOUS SLAVE

RECEPTION

The operation of the Synchronous Master and Slave

modes is identical, except in the case of Sleep or any

Idle mode and bit SREN, which is a “don’t care” in

Slave mode.

If receive is enabled by setting the CREN bit prior to

entering Sleep or any Idle mode, then a word may be

received while in this low-power mode. Once the word

is received, the RSR register will transfer the data to the

RCREG register. If the RCIE enable bit is set, the

interrupt generated will wake the chip from the low-

power mode. If the global interrupt is enabled, the

program will branch to the interrupt vector.

To set up a Synchronous Slave Reception:

Enable the synchronous master serial port by

setting bits SYNC and SPEN and clearing bit

CSRC.

If interrupts are desired, set enable bit RCIE.

If 9-bit reception is desired, set bit RX9.

To enable reception, set enable bit CREN.

Flag bit RCIF will be set when reception is

complete. An interrupt will be generated if

enable bit RCIE was set.

Read the RCSTA register to get the ninth bit (if

enabled) and determine if any error occurred

during reception.

Read the 8-bit received data by reading the

RCREG register.

If any error occurred, clear the error by clearing

bit CREN.

If using interrupts, ensure that the GIE and PEIE

bits in the INTCON register (INTCON<7:6>) are

set.

TABLE 15-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Values

on page

INTCON

GIE/GIEH PEIE/GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

PIR1

—

ADIF

RCIF

TXIF

—

CCP1IF

TMR2IF

TMR1IF

PIE1

—

ADIE

RCIE

TXIE

—

CCP1IE

TMR2IE

TMR1IE

IPR1

—

ADIP

RCIP

TXIP

—

CCP1IP

TMR2IP

TMR1IP

RCSTA

SPEN

RX9

SREN

CREN

ADDEN

FERR

OERR

RX9D

RCREG

EUSART Receive Register

TXSTA

CSRC

TX9

TXEN

SYNC

SENDB

BRGH

TRMT

TX9D

BAUDCON

ABDOVF

RCIDL

—SCKP

BRG16

—

WUE

ABDEN

SPBRGH

EUSART Baud Rate Generator Register High Byte

SPBRG

EUSART Baud Rate Generator Register Low Byte

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.

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